1. Field of the Invention
The present invention relates to a semiconductor device incorporating a semiconductor constructing body, and a method of fabricating the same.
2. Description of the Related Art
Recently, a semiconductor device called a CSP (Chip Size Package) is developed as the downsizing of portable electronic apparatuses such as cellular phones advances. This CSP is obtained by forming a passivation film (intermediate insulating film) on the upper surface of a bare semiconductor device having a plurality of connecting pads for external connection, forming holes in those portions of the passivation film, which correspond to the connecting pads, forming interconnections to be connected to the connecting pads through these holes, forming columnar external connection electrodes on the other end portions of the interconnections, and filling a sealing material between the external connection electrodes.
Solder balls are formed on the columnar external connection electrodes of this CSP, and then the CSP can be bonded to a circuit board having connecting terminals by a face down method, so the mounting area can be made substantially the same size as the bare semiconductor device. Therefore, compared to a face up bonding method using conventional wire bonding or the like, the electronic apparatus can be greatly downsized.
A semiconductor device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-168128 is an example of this CSP. The semiconductor device described in this prior art reference is fabricated by a method in which a passivation film, interconnections, external connection electrodes, and sealing material are formed on a semiconductor substrate in the form of a wafer, solder balls are formed on the upper surfaces of the external connection electrodes not covered with the sealing material but exposed, and the semiconductor substrate is cut along dicing lines. Accordingly, not only the size can be decreased to a just chip size separated by dicing, but also the productivity can be increased because the number of steps can be largely reduced.
In recent years, downsizing of semiconductor devices is increasingly demanded with advancing downsizing of products such as cellular phones, and the degree of integration of semiconductor devices is more and more increasing. With this increase in integration degree of semiconductor devices, the number of external connection electrodes increases, and this poses the following problems. In the CSP as described above, the external connection electrodes are arranged on the upper surface of a bare semiconductor device, so the electrodes are generally arranged in a matrix. In a semiconductor device having a very large number of external connection electrodes, therefore, the size and pitch of the external connection electrodes extremely decrease. This makes it impossible to fabricate a CSP in which the number of external connection electrodes is large compared to the size of a bare semiconductor device. That is, if the size and pitch of external connection electrodes extremely decrease, alignment with a circuit board becomes difficult. This also poses fatal problems that, e.g., the junction strength becomes insufficient, the external connection electrodes shortcircuit during bonding, and the electrodes are destroyed by stress produced by the difference between the linear thermal expansion of the semiconductor substrate which is usually a silicon substrate and that of the circuit board.
Also, as described above, the conventional semiconductor device can be bonded to a circuit board by the face down method, so the mounting area can be made substantially the same size as the bare semiconductor device. Therefore, the electronic apparatus can be greatly downsized compared to the face up bonding method using conventional wire bonding or the like, but this downsizing is still limited.
That is, since the CSP is bonded to a circuit board by the face down method, the surface opposite to the connection pad formation surface of the bare semiconductor device is the upper surface. To connect this surface to ground of the circuit board, a dedicated connecting part is formed outside the CSP, and this limits the downsizing. Also, the wiring length increases because this connecting part is formed outside the CSP. Since this poses a problem such as an increase of the impedance (e.g., stray capacitance), the circuit characteristics deteriorate in some cases.